Conventionally, circuits that employ diodes or circuits that employ field-effect transistors (FETs) have been known as switch circuits for passing or blocking a high-frequency signal.
FIG. 1 shows a switch circuit of the background art that uses FETs, this FIG. 1 being a circuit diagram showing the configuration of a SPDT (Single-Pole Double-Through) switch circuit.
The SPDT switch circuit shown in FIG. 1 is provided with a first switch unit 21 and a second switch unit 22 of the SPST (Single-Pole Single-Through) for passing or blocking a high-frequency signal.
First switch unit 21 is connected between first high-frequency terminal 1 and second high-frequency terminal 2 that receive and supply a high-frequency signal, and second switch unit 22 is connected between first high-frequency terminal 1 and third high-frequency terminal 3 that receive and supply a high-frequency signal. First high-frequency terminal 1 is common to first switch unit 21 and second switch unit 22.
First switch unit 21 is of a configuration provided with a plurality of FETs connected in a series (in FIG. 1, three FETs 31-33), the two ends of this series being connected to high-frequency terminals 1 and 2, respectively. FETs 31-33 are connected in a series, the drain or source of one of FETs 31-33 being common to the source or drain of a neighboring one of FETs 31-33. The gate electrode of each of FETs 31-33 is connected to control terminal 11 by way of a respective one of resistance elements 41-43.
Similarly, second switch unit 22 is of a configuration provided with a plurality of FETs connected in a series (in FIG. 1, three FETs 34-36), each of the two ends of this series being connected to a respective one of high-frequency terminals 1 and 3. FETs 34-36 are connected in a series, the drain or source of one of FETs 34-36 being common to the source or drain of a neighboring one of FETs 34-36. The gate electrode of each of FETs 34-36 is connected to control terminal 12 by way of a respective one of resistance elements 44-46.
The gate electrodes of FETs 31-36 that are used in the switch circuit are typically formed with a large gate width, and a high resistance of several kΩ-several hundred kΩ is used in resistance elements 41-46 that are connected to the gate electrodes.
FIG. 2 is a plan view showing the configuration of an FET provided in the switch circuit shown in FIG. 1.
As shown in FIG. 2, the FET is of a configuration provided with drain 161, source 162, and gate electrode 151 formed on conductive channel 141. Resistance element 171 is connected to gate electrode 151 by way of through-hole 181.
When the FET shown in FIG. 2 is connected in a series as in the circuit shown in FIG. 1, source 162 should be common to the drain of the adjacent FET, and drain 161 should in turn be common to the source of the adjacent FET. In addition, resistance element 171 should be connected between the gate electrode of each FET and the control terminal (control terminals 11 and 12 shown in FIG. 1).
As described hereinabove, in an SPDT switch circuit, the gate width of each FET is formed large, resulting in an increase in parasitic capacitance and a deterioration of switch characteristics. Deterioration in characteristics is therefore suppressed in the configuration shown in FIG. 2 by arranging the gate electrode in a known meandering shape.
Explanation next regards the operation of the switch circuit of the background art shown in FIG. 1.
In the switch circuit shown in FIG. 1, the input of a high-level or a low-level control signal to control terminal 11 provided in first switch unit 21 and control terminal 12 provided in second switch unit 22 controls the ON/OFF of first switch unit 21 and second switch unit 22. If complementary input of high-level and low-level binary control signals is applied to control terminal 11 and control terminal 12 at this time, the high-frequency signal that was applied as input from first high-frequency terminal 1 can be supplied as output from second high-frequency terminal 2 or third high-frequency terminal 3, and one of the high-frequency signals applied as input from second high-frequency terminal 2 and third high-frequency terminal 3 can be supplied as output from first high-frequency terminal 1.
However, the properties demanded of a switch circuit such as shown in FIG. 1 include low transmission loss of the high-frequency signal and high isolation across high-frequency terminals. In addition to these properties, low nonlinear distortion is also crucial.
Nonlinear distortion generated in a switch circuit is present in the nonlinear characteristics provided by the various elements of a switch circuit. In particular, in a multiport switch circuit such as a one-input n- (where n is a positive integer) output SPnT switch circuit or an n-input m- (where m is a positive integer) output nPmT switch circuit, there are more signal paths in the OFF state than signal paths in the ON state, and the signal paths in the OFF state are therefore the chief source of nonlinear distortion. This nonlinear distortion is generated because the capacitance of the FET in the OFF state is greatly changed by the potential of the high-frequency signal applied to the FET. In particular, of the nonlinear distortion, even-order distortion such as secondary harmonic distortion (2f0 distortion) or secondary intermodulation distortion (IMD2 distortion) is generated because the impedance when a positive potential is applied to an FET in the OFF state and impedance when a negative potential is applied change asymmetrically. The positive potential here described refers to a normal-direction potential with respect to a prescribed direct-current potential and the negative potential refers to a negative-direction potential with respect to the direct-current potential. This direct-current potential is not necessarily the ground potential.
In a FET in the OFF state, the gate-source capacitance (Cgs) and gate-drain capacitance (Cgd) each vary in response to the change in applied potential as shown in FIG. 3. This shows that the values of Cgs and Cgd also vary when the high-frequency signal applied from the high-frequency terminal changes in the normal direction and negative direction taking the direct-current potential as a reference. In the case of characteristics in which Cgd and Cgs do not intersect at the direct-current potential of the high-frequency signal due to, for example, divergence in the alignment of exposure at the time of fabrication of the FET, the impedance of the FET changes asymmetrically with the direct-current potential as a reference when a high-frequency signal is applied, and different voltage amplitudes are distributed across the gate-drain and across the gate-source, resulting in the occurrence of even-order distortion. Still further, when resistance elements are connected to the FET, the impedance of these elements also changes asymmetrically with the direct-current potential as a reference.
A FET in the OFF state can be considered equivalent to a capacitance element, and the above-described “asymmetrical change in impedance” can therefore be thought of as an asymmetrical change of the capacitance of the FET. However, in the switch circuit of the background art shown in FIG. 1, resistance elements 41-46 are connected to the gate electrodes of each of FETs 31-36 to prevent leakage of a signal from the gate electrode to the control terminal. Accordingly, the influence of the impedance of these resistance elements 41-46 cannot be ignored.
However, in the switch circuit of the background art, increasing the value of each of resistance elements 41-46 that are connected to the gate electrodes of the FETs allows the influence of the impedance of these elements to be ignored.
Japanese Patent Laid-Open No. 2005-341485 (hereinbelow referred to as Patent Document 1) discloses a configuration provided with two parallel signal paths for canceling the distortion component by inverting the phase of the distortion component of one signal path and then adding the distortion components of the two signal paths. In addition, Japanese Patent Laid-Open No. 2006-042138 (hereinbelow referred to as Patent Document 2) discloses a configuration for reducing the strength of the distortion component of a desired frequency by optimal setting of the length of the signal path, and Japanese Patent Laid-Open No. 2005-323030 (hereinbelow referred to as Patent Document 3) proposes a configuration for limiting the generation of distortion by stabilizing the voltage that is applied across the drain and source of an FET.
Still further, Japanese Patent Laid-Open No. 2000-223902 (hereinbelow referred to as Patent Document 4), Japanese Patent Laid-Open No. 2005-065060 (hereinbelow referred to as Patent Document 5), Japanese Patent Laid-Open No. 2005-072993 (hereinbelow referred to as Patent Document 6), Japanese Patent Laid-Open No. 2005-086420 (hereinbelow referred to as Patent Document 7), Japanese Patent Laid-Open No. 2006-211265 (hereinbelow referred to as Patent Document 8), Japanese Patent Laid-Open No. 2007-073815 (hereinbelow referred to as Patent Document 9), and Japanese Patent Laid-Open No. 2007-258766 (hereinbelow referred to as Patent Document 10) disclose configurations in which a capacitance element or resistance element is connected across the gate and drain or the gate and source of an FET to decrease loss or distortion of a switch circuit.
Japanese Patent Laid-Open No. 2006-211265 (hereinbelow referred to as Patent Document 11) discloses a configuration in which, based on the premise that reducing distortion necessitates the suppression of variation of Vgs of an FET, a circuit composed of FETs, resistance elements and capacitance elements is connected between the high-frequency terminal and gate electrode of an FET.
Japanese Patent Laid-Open No. 08-307232 (hereinbelow referred to as Patent Document 12) and Japanese Patent Laid-Open No. 09-018315 (hereinbelow referred to as Patent Document 13) disclose configurations for broadening the power range of a high-frequency signal that normally operates without saturation; and Japanese Patent No. 003813869 (hereinbelow referred to as Patent Document 14) discloses the reduction of distortion by correcting the asymmetry of capacitance.
Japanese Patent Laid-Open No. 2008-017416 (hereinbelow referred to as Patent Document 15) discloses a configuration that realizes the reduction of transmission loss of a high-frequency signal, the improvement of isolation properties between high-frequency terminals, and the reduction of distortion by turning ON/OFF the connection of a resistance element inserted between a control terminal and the gate electrode of an FET to change the resistance.
Of the switch circuits of the above-described background art, the configuration disclosed in Patent Document 1 requires the provision of a plurality of signal paths (wiring), and therefore suffers from the drawback of increased layout area. The configuration disclosed in Patent Document 1 suffers from the additional problem that the distortion component of frequencies close to that of the input signal cannot be eliminated.
The configuration disclosed in Patent Document 2 enables reduction of distortion of a desired frequency, but because the distortion component occurs at only one frequency, cannot be applied to the reduction of distortion components that occur at a plurality of frequencies.
The configuration disclosed in Patent Document 3 stabilizes switch operation by stabilizing the voltage applied across the drain and source of an FET. However, the effect of limiting even-order distortion cannot be obtained by the configuration disclosed in Patent Document 3.
The configurations disclosed in Patent Documents 4, 5, 6, 7, 8, 9, and 10 broaden the power range of a high-frequency signal that normally operates without saturation and can thus reduce the distortion that occurs when a high-power high-frequency signal is applied as input. In other words, the configurations disclosed in Patent Documents 4 to 10 are not intended for the reduction of distortion that occurs when a high-frequency signal is applied as input at power that is within normal operating range without saturation. In addition, the configurations disclosed in Patent Documents 4 to 10 sometimes exhibit even greater distortion due to the addition of resistance elements and capacitance elements in the direction in which the impedance, as seen from a high-frequency terminal, changes asymmetrically with the direct-current potential as reference.
The configurations disclosed in the above-described Patent Documents 1 to 10 do not eliminate the generation source of distortion itself and are therefore prone to problems such as a limited amount of reduction of distortion or the deterioration of other characteristics.
The configuration disclosed in Patent Document 11 suppresses variation of Vgs to suppress variation of the capacitance of an FET resulting from change in the bias voltage, but the effect of reducing distortion is insufficient because variation of not only the Vgs but also the Vgd must be suppressed in order to suppress variation of the capacitance of an FET.
The configurations disclosed in Patent Documents 12 and 13 are directed to broadening the power range of a high-frequency signal that normally operates without saturation and is not intended for reducing distortion that occurs when a high-frequency signal is applied as input at power within a normal operating range and that is not saturated.
Patent Document 14 describes the correction of the asymmetry of capacitance to reduce distortion but makes no disclosure regarding the generation source of distortion and therefore does not adequately describe how capacitance can be made symmetrical. In addition, the configuration disclosed in Patent Document 14 suffers from the problem of increased power consumption due to the flow of current between control terminals by way of interposed resistance elements.
The configuration disclosed in Patent Document 15 employs an FET that is a nonlinear element to realize variable resistance and therefore suffers from the problem that distortion is made even greater.